Stop Update and Start FPGA without stopping Front End VI

[ZGWSU]

I have been working on a project for generation of waveforms using a PXIe-7961R FPGA using both a fixed clock and varriable clock generated by a PXI-5406 function generoator. I control both these systems from a front end VI that feeds the desired values to the FPGA and Function geneorator. Currently when I update the values I have to stop the FPGA and Function genorator with buttons then stop the main VI, start the main VI then start the FPGA (which will automaticly trigger the function generator). Is there a way that I can keep the main VI going at all times? I would still need to update the values going to the FPGA and list going to the function genorator as well as stop and start them to keep them in sync. However, not stopping the front end VI would have major bennifits for this project.

Thanks,

ZG

[RavensFan]

You can send a command to the FPGA to stop its running while loops.  That may be as simple as sending a True to the Stop control on the FPGA.

To restart, use the Run command on the FPGA reference wire.

Here is an example of a VI that contains both of those functions.

[ZGWSU]

I have a similar thing to that where I have a case structure to start and stop. Start contains the Run Invoke Method, false contains reset and abort. the FPGA vi has a flat sequence to start the function generator as well. I have added a stop to the last loop of the FPGA and tried the system, however it does not pass the new data into the fpga. 

[RavensFan]

We would need to see your VI's before we can help you further.

[ZGWSU]

I have attached example VIs of how it works in general.

[RavensFan]

Couple odd things I see.

You have a boolean set to switch when pressed called start/stop.  But the start would be "True" and should really be called Run.  The False case you really be called "Not Run".  Because of the action, if you make the button true, it will continually execute the Run Node.  I don't know what happens if you try to run something that is already running on the FPGA, but it is not logical.  For the False case, it will continually execute the Reset and Abort functions.  (it would probabaly make slightly more sense if you aborted THEN reset.)

You don't have any way of just having the thing run with out continually Starting, or continually resetting and aborting.

In your FPGA code, you loop in the first frame until IO Module IO Enabled becomes true.  Wait 10 seconds.  Then run frame 3 for 200 iterations of that loop pumping out effectively a digital pulse.  That will happen in 2.5 microseconds with the 80 MHz clock..  then in frame 4 you read the Waveform and run a loop forever (until you hit abort.  Actually Abort is redundant because the Reset node says it aborts and resets.  The problem with reset is it returns the values to default.  So perhaps that is why you never see the waveform values change.  They go back to default.   The other thing is that your waveform indicators in your main VI only get read when the VI starts.  So stopping and starting within that loop doesn't change the values.  Not until you actually stop your main VI and then restart it.

That is how your code appears to run to me.  (I can't actually run it because I don't have an FPGA to deploy to.)  Now I don't what you are really trying to do here.  But hopefully that analysis of your code will help you figure out why it isn't doing what you are trying to make it do.