Hi everyone, I'm having problems with a LabVIEW 8.6.1 FPGA compile. The VI
in question uses a 24MHz derived clock to run a timed loop containing an IP
core created using Xilinx System Generator with 3 FIFOs (target-scoped, block
memory) being used to pass data between another loop running at 200kHz and the
timed loop. We're 99.9% sure that the IP core should compile so the problem is
coming from the LabVIEW end of things.
Upon compiling, the following error is returned:
* TS_window_Clk40Derived3x5ClkFXFromDCM0 = | SETUP | -122.596ns| 163.841ns| 63| 7613992
PERIOD TIMEGRP "window_Clk40Deriv | HOLD | 0.070ns| | 0| 0
ed3x5ClkFXFromDCM0" TS_Clk40 / 0.6 HIGH 5 | | | | |
0% | | | | |
........
PAR done!
ERROR:Xflow - Program par returned error code 31. Aborting flow execution...
As you can see, the constraint is being missed by a huge margin (equivalent
to about 2.9 ticks of the 24MHz clock) which makes me think that it has to be
an erroneous constraint.
A similar issue is reported at
http://digital.ni.com/public.nsf/allkb/F0D899BED0B128E4862574C8007A75B8 but
this has not solved my problem. Does anyone have any ideas what might be
causing this error?
Thanks,
Andy
