USRP Software Radio

cancel
Showing results for 
Search instead for 
Did you mean: 

External Trigger based data acquisition

We are using USRP-RIO streaming example and want to acquire data based on external trigger.
Our input signal is pulsed generated by a signal generator. Along with RF pulse, a LVTTL Trigger is also generated by a signal generator and both of them are synchronized in time.
Pulsewidth=4usec
Pulse Period=300 uses

I have connected both of them with USRP-RIO and run the streamibg example. Trigger settings in exampme was changed to external-trigger.
Then i observed the output on graph. As expected the RF pulse power was in the start of the graph and was static showing that data is being acquired based on trigger rising edge. But there are still two problems
1: The RF pulse is not exactely at 1st sample and the initial delay varies randomly at differnt runs of program. But during a single run, the delay remains constant.
2: Sometimes the RF pulse starts running on graph showing that data is not not acquired properly based on trigger edge.

We also have a VST 5644 with us. We tested the same setup with VST streaming example and the behaviour of acquired data based on external trigger is totally correct.
so it seems that streaming example code of USRP -RIO might have some issue with causes inaccurate acquisition based on external trigger.

Thanks,
Adeel
0 Kudos
Message 1 of 11
(6,798 Views)

Hi AdeelAnwar,

What version of NI-USRP are you using, and how are you connecting your signal to the USRP-RIO? 

What VI are you opening within the USRP Streaming project - and where are you modifying the trigger to be an external trigger?

Thanks!

Rick C.
0 Kudos
Message 2 of 11
(6,780 Views)
Hi Eccent,

I am using NI USRP 14.0 with labview 2013.
Rf out of signal generator is connected to USRP RX port. Trigger out of signal generator is connected with USRP-RIO DIO-0.
Main host VI of sample project. "Software Trigger" drop down menu was changed to "External Trigger" and Rx mode to "Burst (Finite samples)"

-Adeel
0 Kudos
Message 3 of 11
(6,775 Views)

Hi Adeel,

I'm having trouble finding the exact VI you're using and settings you're changing. In order to create a USRP RIO sample streaming project, I load LabVIEW, select "Create Project", select "NI-USRP" in the left pane, and open the "Simple NI-USRP Streaming" example. 

I then have this project window:

Project window.PNG

 

Is your project similar? And if so, which VI are you changing your settings in?

 

Rick C.
0 Kudos
Message 4 of 11
(6,759 Views)

Hi Rick,

 

I am using "Rx Streaming (Host)" vi. with the settings shown in figure below. Sampling-rate is 3.125 MSPS and num-samples=1040.

I have also attached the figure of "Start-Trigger" which is a subVI of "Streaming XCVR FPGA", where AUX I/O-0 is acts as the source of trigger when we select "Digital-Edge" in the Host VI.

 

Thanks,

    Adeel

0 Kudos
Message 5 of 11
(6,748 Views)

Hi Adeel,

I was able to find the settings - thanks for those images!. Now let's talk about the two issues you were having:

1: The RF pulse is not exactely at 1st sample and the initial delay varies randomly at differnt runs of program. But during a single run, the delay remains constant.

 

When you say "not exactly" at the first sample, do you mean that you receive multiple digital edges before acquisition begins, or there's a delay from the rising edge of the trigger? For the delay that you're seeing, how much of a delay, in general, do you see?

 

2: Sometimes the RF pulse starts running on graph showing that data is not not acquired properly based on trigger edge.

 

Could you elaborate on this? Perhaps some images of what you're trying to describe could be helpful as well.

 

Thanks.

Rick C.
0 Kudos
Message 6 of 11
(6,723 Views)
Hi Rick,

Signal generator is generating RF-pulse and a TTL Trigger. Both of them start and end at the same time. I hv checked this using an Oscilloscope.
I am giving both of these signal to USRP-RIO. Ideally the RF pulse should start on 1st sample of the acquired burst bcz the input digital trigger is synchronized with it. This doesnot happen instead RF-pulse starts after initial "k" samples where k depends on the sampling-rate. Currently i am using 3.125MSPS and acquired RF-pluse is being observed using waveform-graph.
I found out that this maybe due to the fractional interpolator/decimator chain which comes after ADC. If this delay remains fixed then this is not an issue as it can be catered of by ignoring initial samples. But there are two problems
1: "K" doesnot remain constant in different runs of program i.e. if i run the streaming example the pulse start maybe after 8 samples. Now if i stop the streaming example and run it again then the pulse start maybe after 12 samples.
Moreover this doesnot happen if i set the sampling-rate to 1MSPS but when i set the samplind rate to 3.135MSPS this happens. (Note external signal from signal generator pulsewidth=10 usec pulse-period=3khz)
As mentioned above that at different runs of Streaming example i observe different "k". But in a single run this delay remains constant.

2: The other problem is that sometimes when this example is running 'k' starts to vary randomly and this causes the displayed RF-Pulse to move back and forth on the waveform-graph.

Thanks,
0 Kudos
Message 7 of 11
(6,685 Views)
When we connect the same signal generator with VST 5644 and use the VST streaming example using same settings then there is also an initial delay of 5 samples but this remains fixed . So ww just ignore the initial 5 sample but we are unable to do so on the USRP-RIO bcz of abovementioed problem
0 Kudos
Message 8 of 11
(6,682 Views)
The FPGA includes an resampler. The internal clock runs at 120 MS/s. It would make sense that 1MS/s would give you a clean trigger because the ratio 1:120 is an integer resample. Sounds like irrational resamples are more problematic?

But 3.135:120 is giving you an offset that could vary by some number of samples, somewhere between 8 and 12 in your testing. Does that sound like the behavior you see?

Does another integer sample rate like 3 or 5 mS/s go back to a fixed k?
0 Kudos
Message 9 of 11
(6,681 Views)
8-12 was just two figure but it sometimes it reaches 100 aswell and sometimes it varioud while running which is a bigger problem. I also mentioned in one of my previos post that there maybe a bug in fpga code if USRP-RIO bcz In VST example we are having no issues
0 Kudos
Message 10 of 11
(6,676 Views)