Ultiboard Mating PCB Design of the new NI GPIC Platform for Energy Applications

[Mahmoud_W]

Hello Circuit Designers,

With the recent release of the new General Purpose Inverter Control (GPIC), I am pleased to introduce you to this new power inverter implementation grabbed the attention of a lot of design experts in the renewable energy segment during NI Week this year.

The general idea is for the Single-Board RIO 9606, the GPIC 9683, and a mating board to form a stack of 3 PCBs for inverter control.  This inverter stack allows the 3 PCBs to act as a single system with multiple functionalities:

1. The Single-Board RIO features a user programmable FPGA and a PowerPC processor. 

2. The GPIC offers a complete set of I/O, using common electronics control applications. The controller and the I/O board are connected together using a RIO Mezzanine Connector (RMC); this provides high speed, high bandwidth length between the I/O on the GPIC and the FPGA on the Single-Board RIO.  

3. The GPIC mating board connects directly to six female Insulation Displacement Connectors (IDC) headers at the bottom of the GPIC and provides connectivity to the 6-pack inverter load, as well as break-out of the simultaneous AIs, scanned AIs, LVTTL DIOs, Sourcing DIs, Sinking and Relay DOs, and Half-Bridge DOs.  The mating board was developed to save you days of development for a custom inverter interface.

The mating PCB for the GPIC platform was fully designed in Ultiboard and a template of that design is made available for all NI power electronics customers HERE!

The features of this example GPIC mating board including the following:

1. Screw terminal breakout connectors for each GPIC I/O connector
2. 26-pin IDC Semikron SKiiP 3 connector, allowing you directly connect to large inverter cables
3. Powered by external 15 VDC regulated supply; extra terminals available for jumpering power to the Single-Board RIO using 2-position mini-fit power plug pigtail wire assembly
4. Shunt resistor pads for all analog inputs
5. Preservation of ground plain and trace keep-out spacing distances for functionally isolated simultaneous analog inputs
6. Relay signals isolated to reduce high current and noise.
7. Digital I/Os matched to traces at certain impedances to account for high speed currents
8. Follows simultaneous analog input pseudo-differential grounding scheme recommendations
9. Thick 0.093” PCB for mechanical strength
10. 0.040” plated holes for SH2 mating connectors for proper IDC connector mechanical alignment
11. Keepout spacing on all sides suitable for extraction crowbar tool
12. Keepout area for HALO transformer; no components can be placed underneath

NI Multisim's team continues to invest in power electronics applications and would be happy to hear your feedback about it.

Mahmoud W

NI